(1) Field of the Invention
The invention relates to a method of forming an inductor in the fabrication of integrated circuits, and more particularly, to a method of forming a high quality inductor using air as a barrier in the manufacture of integrated circuits.
(2) Description of the Prior Art
The integration of radio frequency (RF) integrated circuits on silicon is one of the greatest challenges for the growing markets of wireless communications. The incorporation of RF inductors on silicon without sacrificing the quality factor (Q) due to substrate losses has been researched heavily in recent years. Some of the techniques include: (i) selectively etching out silicon under the inductor by micro-machining, (ii) employing multi-metal layer of aluminum interconnects or copper damascene interconnects, (iii) using a high resistivity silicon substrate, (iv) employing a biased well underneath a spiral inductor, (v) inserting various types of patterned ground shield between the spiral inductor and the silicon substrate, and (vi) increasing the thickness of the interlayer dielectric. This is not an exhaustive listing. The common objectives of all of these techniques are: 1) to enhance the Q value of the inductor and 2) to increase the self-resonance frequency so that the usable frequency range of the inductor is widened.
The self-resonance caused by the parasitic capacitance of the spiral inductor to the silicon substrate will limit the use of these inductors at high frequencies. The increasing series spreading resistance will degrade the Q factor. This impacts the usefulness of integrated spiral inductors implemented on silicon substrates. These problems can be overcome if the area under the inductor is made to appear locally insulating by selectively removing the underlying silicon resulting in inductors "hanging" in air. Air, which has the lowest dielectric constant, is the most ideal barrier. However, micro-machining, used to etch away the silicon under the inductor, is complex and is not compatible with any normal process flow. It is desired to utilize air as a barrier in a process that is implemented easily and is compatible with any process flow with minimal changes.
U.S. Pat. No. 5,539,241 to Abidi et al shows a method of etching out a pit under an inductor during CMOS processing. U.S. Pat. No. 5,844,299 to Merrill et al shows an inductor formed over a pit containing silicon oxide. U.S. Pat. No. 5,742,091 to Hebert et al teaches deep trenches filled with a low dielectric constant material. U.S. Pat. No. 5,773,870 to Su et al discloses backside etching of the substrate under an inductor. U.S. Pat. No. 5,770,509 to Yu et al teaches another inductor process.